FPGA testing using pipelined error-detecting codes
Published: 18.11.2013
Authors: Brekhov O.M., Ratnikov M.O.
Published in issue: #11(23)/2013
DOI: 10.18698/2308-6033-2013-11-1005
Category: Information technology
In this article approach to the solution of FPGA testing and research of characteristics at early development stages is offered. Within this approach universal test firmware based on pipelined control codes generators are offered. Test firmware based on CRC are realized - reveals single and multiple faults and Hamming’s code - reveals a fault or refusal place.